1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a power device driving device for driving power devices, e.g. inverters.
2. Description of the Background Art
A power device includes series-connected first and second N-channel insulated-gate bipolar transistors (IGBTs) and a power device driving device. The first IGBT has its collector electrode connected to a main power-supply and the second IGBT has its emitter electrode connected to a ground potential. The emitter electrode of the first IGBT and the collector electrode of the second IGBT are connected to a load. Free-wheeling diodes are connected in inverse-parallel respectively to the first and second IGBTs in order to protect the first and second IGBTs from counterelectromotive force due to the load.
The power device driving device includes a high-voltage-side driving portion for controlling the first IGBT and a low-voltage-side driving portion for controlling the second IGBT. The power device driving device has a VS terminal connected to the emitter electrode of the first IGBT, a VB terminal connected to the emitter electrode of the first IGBT through a capacitor, an HO terminal connected to the control electrode of the first IGBT, a COM terminal connected to the emitter electrode of the second IGBT, a VCC terminal connected to the emitter electrode of the second IGBOT through a capacitor, an LO terminal connected to the control electrode of the second IGBT, and a GND terminal. VS denotes a high-voltage-side floating offset voltage that serves as a reference potential for the high-voltage-side driving portion. VB is a high-voltage-side floating supply absolute voltage serving as a power-supply for the high-voltage-side driving portion, which is supplied from a high-voltage-side floating power-supply. HO is a high-voltage-side driving signal output by the high-voltage-side driving portion. COM is common ground. VCC is a low-voltage-side fixed supply voltage serving as a power-supply for the low-voltage-side driving portion, which is supplied from a low-voltage-side fixed supply power-supply. LO is a low-voltage-side driving signal output by the low-voltage-side driving portion. GND is a ground potential.
Now, the conventional power device driving device, specifically the high-voltage-side driving portion, is described.
The high-voltage-side driving portion includes a CMOS circuit having PMOS and NMOS transistors. The PMOS transistor has its source electrode connected to the VB terminal, the NMOS transistor has its source electrode connected to the VS terminal, and the PMOS and NMOS transistors have their respective drain electrodes connected to the HO terminal.
Next, the structure of the conventional semiconductor device having the CMOS circuit is described. The semiconductor device has a p−-type silicon substrate, an n-type impurity region formed in the upper surface of the p−-type silicon substrate, a p-type well formed in the upper surface of the n-type impurity region, n-type source and drain regions of the NMOS transistor that are formed in the upper surface of the p-type well, p-type source and drain regions of the PMOS transistor that are formed in the upper surface of the n-type impurity region, and a p+-type isolation region formed in the upper surface of the p−-type silicon substrate and in contact with the n-type impurity region.
A channel formation region is defined between the source and drain regions of the NMOS transistor and a gate electrode of the NMOS transistor resides on the channel formation region with a gate insulating film disposed between them. Likewise, a channel formation region is defined between the source and drain regions of the PMOS transistor and a gate electrode of the PMOS transistor resides on the channel formation region with a gate insulating film disposed between them. The source region of the NMOS transistor is connected to the VS terminal and the source region of the PMOS transistor is connected to the VB terminal. The drain regions of the NMOS and PMOS transistors are connected to the HO terminal in common.
Techniques about semiconductor devices having CMOS circuits are disclosed in Japanese Patent Application Laid-Open Nos. 11-68053 (1999), 62-120063 (1987), 60-74560 (1985), and 5-152523 (1993).
In the conventional power device and power device driving device, the high-voltage-side floating offset voltage VS may vary to a negative voltage lower than the common ground COM during regenerative periods (i.e. periods in which free-wheeling diodes turn on due to the counterelectromotive force from the load). The negative variation of the high-voltage-side floating offset voltage VS is transmitted to the high-voltage-side floating supply absolute voltage VB through the capacitor and then the potential of the high-voltage-side floating supply absolute voltage VB, too, makes a negative variation.
The negative variation of the high-voltage-side floating supply absolute voltage VB is transmitted to the n-type impurity region. As a result, parasitic diodes between the p+-type isolation region and n-type impurity region and parasitic diodes between the p−-type silicon substrate and n-type impurity region, which are normally reverse-biased, turn on, which causes current to flow into the n-type impurity region.
Then, in the conventional semiconductor device, the current flowing into the n-type impurity region due to the turning-on of the parasitic diodes may cause the high-voltage-side driving signal output HO to be logically inverted (malfunction), or may cause a parasitic thyristor to latch up to cause excessive current flow to the CMOS circuit, which may damage the circuitry or parts (latchup breakdown: for more details, refer to Japanese Patent Application Laid-Open No. 2002-252333 by the same applicant).